1. Field of the Invention
The present invention relates generally to the field of semiconductor process. More particularly, the present invention relates to a trench isolation process that utilizes spacer process and/or thermal oxidation to achieve void-free trench fill.
2. Description of the Prior Art
In the application of the integrated circuit, the different functional elements are often built on a single chip. In order to ensure that each individual component does not interfere with other components around, the electrical isolation between circuit components is particularly important.
Local oxidation of silicon (LOCOS) is a well known and common isolation method. The LOCOS process is not complex, and has the advantage of low cost. However, with the progress of process capability as well as scaling of elements, the problems such as bird's beak and field oxide thinning have become worse. Therefore, shallow trench isolation (STI) process has been developed.
The STI process includes first etching trench around the active area and then filling the trench with insulating material to isolate the active area. Although the shortcomings of LOCOS can be overcome by the STI process, but it also has the problems of dishing effect and sub-threshold kink effect. Further, with the components miniature, void-free trench fill has become more difficult to achieve.